1. Technical Field
This invention relates to the testing of integrated circuit memories and more particularly to automatic generation of a customized test program for testing a memory array on a selected tester.
Integrated circuit memory arrays are widely used for storing data in data processing systems. As is well known to those skilled in the art, an integrated circuit memory typically comprises a plurality of memory cells arranged in an array or matrix having a predetermined number of rows and columns, with one data bit being stored per cell. Data is typically written into or read from the array by addressing one or more cells and reading or writing the desired data.
2. Background Art
In the current state of the art, two hundred fifty-six thousand or more cells may be integrated on a single semiconductor substrate. Such arrays present extreme problems in the testing environment.
Among the tests typically performed on an array are DC parametric tests, AC parametric tests and AC pattern tests. DC parametric tests relate to static electrical properties such as voltage or current limits for the array cells and connecting lines. DC parametric tests may be performed on integrated circuits having interconnected memory cells thereon, (i.e., product tests) or on integrated circuits having unconnected devices thereon (i.e., test site tests). AC parametric tests relate to dynamic electrical properties such as minimum bit/word address access time, and minimum cell switching transition times. AC pattern tests read and write various well known test patterns into the array to ensure that each cell is functioning properly and is not disturbed by operations performed on other cells. Examples of well known AC pattern tests are walking 1's, marching 1's, or checkerboard pattern tests. Memory testers typically include a tester memory for storing therein an instruction sequence representing all of the tests to be performed on the array, and a tester pattern generator for generating the appropriate address, control and data signals from the stored instruction sequence in the tester memory.
From the above description it will be appreciated that for a large array, generation of the requisite tester memory instruction sequences is inordinately complex and time consuming. The instruction sequences for the tester memory must be created and debugged manually, a process that may take weeks when dealing with a two hundred fifty-six thousand bit array. Moreover, in order to properly generate the instruction sequence, the test designer must be intimately familiar with the configuration of the tester being employed and the instruction set therefor. Further, an array manufacturing facility may often employ a number of different memory testers each having different instruction sets. Memory test data must be created anew when another tester is employed, since there is usually no software compatibility even between different types of memory testers from the same manufacturer. Accordingly, additional weeks of test generation and debugging may be required when it is desired to add or change testers array.
State of the art memory testers have attempted to alleviate some of the manual work of creating an appropriate tester instruction sequence by designing the tester to accept a higher level instruction set. However, such high level instructions are still tester dependent, i.e., they are particular to a given tester. Thus, the test designer must be intimately familiar with the high level instruction set for each tester being employed. Moreover, the high level instruction sequence that defines the test program must be created anew when a different tester is employed. Accordingly, while the high level language provisions of state of the art memory testers have eliminated some of the more tedious work, they have not solved the problems faced in a manufacturing environment which must test many array types on a plurality of different array testers.